@WTCON 0x53000000

@BWSCON   0x48000000
@BANKCON0 0x48000004
@BANKCON1 0x48000008
@BANKCON2 0x4800000C
@BANKCON3 0x48000010
@BANKCON4 0x48000014
@BANKCON5 0x48000018
@BANKCON6 0x4800001C
@BANKCON7 0x48000020
@REFRESH  0x48000024
@BANKSIZE 0x48000028
@MRSRB6   0x4800002C
@MRSRB7   0x48000030

.equ	MEM_CTL_BASE,	0x48000000
.equ	SDRAM_BASE,		0x30000000

.text
.global _start
_start:
	bl disable_watch_dog
	bl memsetup
	bl copy_steppingstone_to_sdram
	ldr pc,=on_sdram

on_sdram:
	ldr sp,=0x34000000
	bl main

halt_loop:
	b halt_loop

disable_watch_dog:
	mov r0,#0x53000000
	mov r1,#0x0
	str r1,[r0]
	mov pc, lr

copy_steppingstone_to_sdram:
	mov r0,#0
	ldr r1,=SDRAM_BASE
	mov r2,#4*1024

1:
	ldr r3,[r0],#4
	str r3,[r1],#4
	cmp r0,r2
	bne 1b
	mov pc,lr

memsetup:
	mov r0,#MEM_CTL_BASE
	adrl r1,mem_cfg_val
	add r2,r0,#52

1:
	ldr r3,[r1],#4
	str r3,[r0],#4
	cmp r0,r2
	bne 1b
	mov pc,lr

.align 4
mem_cfg_val:
	.long 0x22011110
	.long 0x00000700
	.long 0x00000700
	.long 0x00000700
	.long 0x00000700
	.long 0x00000700
	.long 0x00000700
	.long 0x00018005
	.long 0x00018005
	.long 0x008C07A3
	.long 0x000000B1
	.long 0x00000030
	.long 0x00000030
